The present invention relates generally to vertical channel electric field controlled semiconductor devices such as field effect transistors and field controlled thyristors and, more particularly, to methods for fabricating buried grids for such devices.
Various forms of vertical channel field controlled semiconductor devices are known. These include field controlled thyristors (FCTs), a variation sometimes termed a field terminated diode (FTD), as well as field effect transistors (FETs). These devices are potentially capable of switching voltages in the order of 50 to 1000 volts, with currents of from 1 to 100 amperes, at frequencies greater than 15 kHz, exceeding the capabilities of conventional bipolar devices.
Such devices are described in the literature, for example, D. E. Houston, S. Krishna, D. E. Piccone, R. J. Finke and Y. S. Sun, "A Field Terminated Diode", IEEE Trans. Electron Devices, Vol. ED-23, No. 8, pp. 905-911. (Aug. 1976). In addition to this Houston et al literature reference, various forms of such devices are disclosed in the commonly-assigned patents to Ferro U.S. Pat. No. 4,037,245, Houston et al U.S. Pat. No. 4,060,821, Baliga U.S. Pat. No. 4,132,996, and Hysell et al U.S. Pat. No. 4,170,019. Additional disclosures are found in commonly-assigned Baliga and Wessels U.S. patent application Ser. No. 169,853 filed July 17, 1980, entitled "PLANAR GATE TURN OFF FIELD CONTROLLED THYRISTORS AND PLANAR JUNCTION GATE FIELD EFFECT TRANSISTORS, AND METHOD OF MAKING SAME", which is a continuation of now-abandoned application Ser. No. 938,020, filed August 30, 1978, in turn a continuation-in-part of now-abandoned application Ser. No. 863,877, filed Dec. 23, 1977.
Briefly, in a thyristor or diode form of a field controlled device, a P+ anode, N- base, and N+ cathode structure is provided, with the N- base region containing a low resistivity P+ grid or gate defining a number of vertical channels. In general, the device functions as a power rectifier with forward blocking capability and gate turn off capabilities. Field effect transistors of similar structure may also be provided, in which case, rather than a P+ anode region there is an N+ drain region.
In plan view, the grid may take a variety of geometric forms. Described herein are grids comprising a plurality of parallel elongated elements, although it will be appreciated that the invention is not so limited.
There are two general structures for these devices: planar structures wherein the grid is on the surface of the device, and buried grid structures wherein the grid is buried within the base region. Buried grid devices have the advantage of increased cathode (or source) area compared to planar devices because, in planar devices, the cathode (or source) region must be located between the grids and sufficiently separated to obtain an acceptably high grid-cathode (or grid-source) breakdown voltage. Buried grid structures overcome this particular problem, and enable a higher blocking gain to be achieved. It should be noted, however, that the inability to metallize a buried gate along its entire length results in higher grid resistance, and thus limits the frequency response of buried grid FETs and FCTs.
A hybrid approach is disclosed in the above-identified commonly-assigned Houston et al U.S. Pat. No. 4,060,821 wherein the grid is divided into surface grid portions and buried grid portions, with the buried grid having a greater lateral extent; at the device surface, the surface area of the cathode structure is substantially greater than that of the grid structure.
The Houston et al literature reference describes both planar grid and buried grid devices, and the fabrication of such devices by means of diffusion technique. In particular, to form a buried grid, an appropriate mask pattern is applied to the surface of an N- type base substrate, and P+ grid regions are diffused into the surface of the base. Thereafter, the grid is covered or buried with N- type layer grown using vapor phase epitaxy. This layer has conductivity essentially identical to that of the base substrate. The base substrate and the epitaxially-grown layer then, together, form the overall base region. Thereafter, the cathode or source region is diffused into the upper surface of the epitaxially-grown layer comprising the base region, and metallization applied to complete the device. Further descriptions of the technique are found in the literature: B. M. Berry, "Epitaxy", Section III, pp. 347-470, in "Silicon Integrated Device Technology", Vol. 1, Edited by R. M. Burger and R. P. Donovan, Prentice-Hall, Inc. (1967); and J. I. Nishizawa, R. Terasaki, and J. Shibata, "Field-Effect Transistor Versus Analog Transistor (Static Induction Transistor)", IEEE Trans. Electron Devices, Vol. ED22, pp. 185-197 (1975).
While described herein primarily in the context of the fabrication of buried grids for electric field devices, it will be appreciated that similar buried regions are found in other devices and integrated circuits and that the techniques described herein are applicable to some of these as well.
One particular and potentially serious problem which arises during the formation of buried grid structures by vapor phase epitaxial growth to bury the grid structure is autodoping. Autodoping is caused by the P+ type dopant of the grid region entering the gas phase during initial stages of epitaxial growth. This can result in a severe distortion in the shape of the buried grid region or, even worse, a short in the form of a connecting layer between the grid regions, preventing the fabrication of the buried grid structure.
One method for avoiding autodoping effects, successfully used in the fabrication of closely spaced buried grid regions and in the development of buried grid field controlled thyristors, is to grow the epitaxial layers from the liquid phase. This is described in the literature: B. J. Baliga, "Buried Grid Fabrication by Silicon Liquid-Phase Epitaxy", Appl. Phys. Lett., Vol. 34, pp. 789-790 (1979) and Appl. Phys. Lett., Vol. 35, p. 647 (1979); and B. J. Baliga, "Power Field Controlled Thyristors Fabricated Using Silicon Liquid Phase Epitaxy", Device Research Conference, Paper WP-B7 (1979); see IEEE Trans. Electron Devices, Vol. ED 26, p. 1858 (1979). Similar disclosures are found in commonly-assigned Baliga U.S. Pat. No. 4,128,440 entitled "Liquid Phase Epitaxial Method of Covering Buried Regions for Devices", and Baliga et al U.S. Pat. No. 4,251,299 entitled "Planar Epitaxial Refill Using Liquid Phase Epitaxy". The present invention, however, is directed to methods employing vapor phase epitaxy to cover buried structures.
As pointed out in the above-identified commonly-assigned application Ser. No. 169,853, another problem is that the shape of a buried grid formed by means of diffusion is somewhat semi-cylindrical, and this results in a poor channel length-to-width ratio. This leads to a relatively poor blocking gain, requiring closely-spaced grids, which in turn, reduce the conduction area of the device.
The above-identified Baliga and Wessels application Ser. No. 169,853, goes on to describe planar, junction gate FETs and FCTs having higher forward blocking capabilities and higher blocking gains than diffused-grid devices. In particular, described are gate or grid regions comprising substantially vertical walls, such that the grids are rectangular in cross-section. As there described, preferential etch and refill techniques are employed to achieve the substantially vertical walls and rectangular cross sections.
Comparisons of surface (planar) grid field controlled devices having grid regions having cylindrically shaped walls fabricated by planar diffusion as described in the Houston et al article entitled, "A Field Terminated Diode" to planar grid field controlled devices including grid regions with vertical walls fabricated using the epitaxial refill technique have shown that a significantly higher blocking gain is observed in the planar devices with vertically walled gate regions. Accordingly, it has recently been recognized that similar improvement in the blocking gain of buried grid devices is to be expected by replacing the conventional cylindrically walled grid regions fabricated by planar diffusion with vertically walled grid regions.
The buried rectangular cross-section grid structure is advantageous compared with the diffused grid structure of the Houston et al literature reference in that grid spacing can be larger due to improved channel length-to-width ratio, resulting in increased active area and reduced forward voltage drop. Compared with the planar grid device of the above-identified commonly-assigned Baliga et al application Ser. No. 169,853, the cathode area is larger. (Grid resistance limitations do, however, remain).